PDK Tutorials

TSMC 65nm

• Creating Libraries and Schematics in Cadence
• Creating Schematics in Cadence
• Creating Testbench
• DC Simulation
• AC Simulation
• Layout Preparation
• Layout Component Placement
• Layout Routing
• Design Rule Check
• Layout Versus Schematic
• Parasitic Extraction and Post-Layout Simulation

TSMC 180nm

• Environment Setup
  
• Schematic Creation in Cadence
• DC Simulation
  • IV Curve Plotting
  • gm Plotting
• AC Simulation
• DC Sweep Simulation
  
• Layout Component Placement and Routing
  
• Design Rule Check
• Layout Versus Schematic
• Parasitic Extraction and Post-Layout Simulation
• GDS File Extraction
• Dummy Metal Filling
• Example: Simulation of a Differential Amplifier

Appendix

• Bindkeys
• Environment Customization
• Troubleshooting
• Guacamole Tutorial
• MobaXterm Tutorial