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Post Layout Simulation

   Authors: Michael Cunningham, Ji Hoon Hyun, Dr. Dong S. Ha

Simulation

  1. Simulation is fairly simple, all you really need to do is switch to the av_extracted view:
     
  2. Go to the Library Manager, select the testbench for your design and add a new cell view (File → New → Cell View...). You can also do this through the icfb window.
PLS-Figure01
Figure 1. New testbench cell view

 
  • In the next window, change the "Tool" to "Hierarchy-Editor". Make sure the "View Name" is now "config".
PLS-Figure02
Figure 2. Create new file
 
  • In the New Configuration window, browse and select the schematic view. Then click the "Use Template..." button and select "spectre" in the new window. Select OK.
PLS-Figure03
Figure 3. New configuration

 
  • The hierarchy editor will populate with cell bindings from the top cell. Select the appropriate cell (your circuit level, not the testbench) and enter "av_extracted" into the "View to Use" box. Save your design using the floppy disk symbol in the top toolbar and close the window.
PLS-Figure04
Figure 4. Cell Hierarchy

 
  • Now go to your testbench schematic and start the Analog Design Environment. Change the "View Name" to config either through Setup → Design... or by pressing the emitter follower symbol on the right toolbar (at the top). You may need to reload your state.
PLS-Figure05
Figure 5. View config

 
  • Now run your simulation and compare the layout to the circuit (use the "Append" feature for the plotting mode and run the simulation each view).
     
    You might get a very poor result (shown below). You will need to fix your layout to reduce parasitic values.
PLS-Figure06
Figure 6. Simulation results

 
  • If you need to fix your layout, do so. Remeber to run RCX again so that the av_extracted view contains the new design. Overwrite the av_extracted view so that it is automatically updated. If you want to keep a previous design, the easiest thing to do is to save the cell as a backup:
PLS-Figure07
Figure 7. Copy cell
PLS-Figure08
Figure 8. New name (e.g. "[cell name]_bu")
PLS-Figure09
Figure 9. View of backup

 
  • Re-simulate with the "config" view. As you can see, increasing the line size and improving the routing can help out the design. This layout still needs some work (large lines have a lot of capacitance and there is still a fair amount of resistance added), but it is nearly there.
PLS-Figure10
Figure 10. Updated simulation


Comments to: ha@vt.edu

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