Design Rule Check

Authors: Michael Cunningham, Joseph Chong, and Dr. Dong S. Ha

Essentially, the DRC will check to make sure that the layout you have made is possible to fabricate according to the foundry rules. There are different ways to run DRC, but we will only discuss the usage of Calibre Interactive here. (See here on how to setup environment for Calibre).

1.  In the layout window, go to Calibre → Run DRC.

2.  If you have already created the runset, skip to Step 9. Otherwise, close the "Load Runset File" form.

3.  In the interactive window, select the "Rules" tab and type (or copy and paste) the following text into the "DRC Rules File" box. Then, select "Load".

NOTE: To paste in Calibre, use "Ctrl + v".

4.  In your terminal, we will make a directory for the drc information to be stored. Type "mkdir drc01" after cdsprj and all other commands.

5.  Change your "DRC Run Directory" to this location so you don't flood your project space with drc files.

6.  Let's save this runset. Go to File → Save Runset.

7.  With the "File Path" empty, press OK.

8.  In the next window, give it a name (e.g. TSMC_65nm_DRC). Select OK.

9.  If you came here from step 2, load the runset we created. Otherwise, continue next step.

10.  Click on the "Inputs" tab and verify that the file information is correct.

11.  Now, select "Run DRC".

12.  Once it is complete (which may take a while, even on campus), a summary file and the Results Viewing Environment (RVE) window will appear.

It is important to note that even though there are a lot of errors, often one fix will solve many other problems.

DRC Debugging

Go to the RVE window. Here, there is a list of errors and a description in the bottom box. For Analog IC Design class, we will only focus on/disregard the following as mentioned. In actual case, it is up to the foundry whether to waive errors or reject your design.

• All "CSR.*" (Corner Stress Relief) errors can be ignored. Metals and vias are not allowed in chip corners, but we are not creating the entire chip. 
• Any "*.EN" (Enclosure) errors regarding chip edge can be waived; all others should be resolved according to the rule described in the explanation window. 
• All "*.S" (Spacing) errors should be resolved. Move metals or vias to meet the minimum spacing requirements. 
• All "*.W" (Width) errors should be resolved. Resize any flagged objects to meet the maximum/minimum width rules.
• All "*.A" (Area) errors should be resolved. Resize the metal/via as described in the check. 
• All "G.*" (Grid) errors should be resolved. The grid is the minimum resolution that can be manufactured. If you used paths with variable ends and specified a length less than the grid resolution (for some unknown reason), you will receive an error. All other path ends are fixed to the grid.
  Additionally, do not change the grid resolution from 0.005 in the layout display options ("e"). 
  
  

• All "IND.DN " (Inductor Density) errors can be waived as this is one segment of a chip. This error is generated if the inductor is too large compared to the chip.
• All ".DN " (Density) errors should be resolved (with the exception of the aforementioned case). Certain metal and oxide densities are required for fabrication. TSMC recommends their autofill script, but I will not cover this as it is better suited for those with sufficient layout experience.
  Alternatively, you can satisfy this error by manually adding in dummy layers of metal - Mx(dm) - thin oxide for device - OD(dm) - and polysilicon oxide - PO(dm) in the empty areas of your chip. This image below is a 4 x 4 array of dummy layers OD, PO, M1, M2, M3, M4, M5, and M6 vertically aligned. Each square is 3μm x 3μm with 3μm spacing.

Once you select a check/cell in the left column, double-clicking or pressing the light button in the toolbar will highlight and zoom in on the error. Follow the description to resolve the error.

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