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      Multifunctional Integrated Circuits and Systems Group (MICS)
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      MICS / IC Design / Tutorials / Cadence 

      Others

      The following tutorials show setup files, basic features and simple examples of Cadence tools for VLSI design.

      Layout Tutorial

      • Layout with Virtuoso
        • Inverter Tutorial with Virtuoso
        • Capacitor and Resistor Layout
        • FAQ about Layout
        • Introduction to SKILL
      • DRC (Design Rule Check) with Virtuoso
      • LVS (Layout-Versus-Schematic) with Virtuoso
      • Logic Simulation with Verilog
        • HSpice Netlist Extraction with Cadence
        • Spectre Netlist Extraction with Cadence
          • Spectre Simulation with Command Line
          • Spectre Simulation with Analog Artisit (Graphical Interface)

      Back-End Design

      • SOC Encounter: Place and Route Tool
      • Import Verilog Netlist into Schematic
      • Import GDS into Cadence Layout
      • Pad Insertion
      • Steps for Chip Submission
      Comments to: ha@vt.edu
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