Design Rule Check (DRC)

Author: Jeannette Djigbenou

There are process-specific design rules that describe how close layers can be placed together and what the sizes of the areas can be. These rules are given the minimum requirement to avoid a catastrophic failure of your circuit due to fabrication faults. You can use the following MOSIS SCMOS design rulesas a guideline. The design rules are different for different processes.

The following is a procedure to perform design rule check (DRC) for a layout. DRC outputs any violations of the design rules for your technology process. This step is important because the violation of any design rules would cause the fabricated chip to not function as desired.

Before you start, you have to have a layout (view name: layout) in your library.

From your Layout window:

1.  Choose Verify -> DRC from the menu. The Verify DRC form will appear.

2.  Set the Switch Names field. This switch name depends on the process you're running.

• For the NCSU Kit and other processes: Leave as default.

3.  Click OK to run DRC.

• If your design has violated any design rules, DRC will reports the errors in the CIW.
• Errors are indicated by the markers (white color) on the circuit.
• You may then proceed to correcting the errors according to the design rules. Explanations about common DRC errors are listed in the FAQ section.

4.  For huge layouts, the marker might not be easily located. To find markers, choose Verify -> Markers -> Find in layout window.

• A pop up menu will appear. Click on the Zoom to Markers box.
• Click on the Apply button and Cadence will zoom in to the errors or warnings as desired.

Have fun!

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