Introduction to the Cadence Tutorial for Digital IC Design

Cadence Tutorials

Front-End

• Compile and Simulate: Use of NC-Verilog® and SimVision to analyze, compile and simulate an example up-down counter
• Synthesis: Convert the Verilog code into gate-level netlist using Cadence’s Encounter™ RTL Compiler
• Power Estimation: TCF file generation and early power estimation of the design using SimVision and RTL Compiler.

Back-End

• Physical Implementation: Floorplanning to place and route of a test circuit using Cadence’s Encounter Digital Implementation.

Digital Design Flow

• Digital Design Flow: Methodology for successful front-end design to back-end implementation of the chip at System on Chip (SoC) level. This involves using different tools from Synopsys and Cadence.