Fron End Design Using Cadence Tool - Part 02 Synthesis (rc)

Authors: Hetaswi Vankani and Dr. Dong S. Ha

Tool: RTL Compiler

1. Synthesize

a. Continue working in the same project directory as the earlier tutorial. The directory is called ‘tut_65nm’ in this tutorial.

b. Make sure you have copied rtl.tcl from the earlier tutorial. You can find the link here: rtl.tcl. This is the source script that has library path, path to Verilog script, synthesis commands.

c. To start RTL Compiler: type ‘rc –gui’. In case, missing libraries are reported, contact sysadmin. The ‘-gui’ options pops RTL GUI. Make sure Xming is running in case of remote connection.

d. In GUI: file → source script → load rtl.tcl → hit ‘OK’

d. On hitting ‘OK’, one should be able to observe the following:

This is the design after synthesis. The explanation of various commands executed can be referred to in the comments in rtl.tcl.

2. Reporting power and area

Power

GUI – If you are using GUI, then follow the steps: Report → Power → Detailed Report

A table as shown in figure 4 will be generated.

Command mode: report power>power.rpt

Following report is generated.

Area

GUI-If you are using GUI, then follow the steps: Report → Netlist → Area