Logic Simulation with Verilog

Authors: Jeannette Djigbenou and Jia Fei

This tutorial shows how to perform logic simulation using Verilog. The procedure is for a quick and simple solution, and it does not explore full feature of Verilog. The example to be used in this tutorial is a 2x1 multiplexer. At this point, you should have set up the environment. Otherwise, refer to Setting Up Your Unix Environment.

Before you start, you have to have a schematic diagram (view name: schematic) of a multiplexer. Each gate symbol used in the schematic diagram should have a switch-level schematic diagram (view name: schematic) in MOSIS library.

If you don't have any of them, refer to previous sections, Gate-Level Schematic Entry with Composer for the gate-level schematic and Switch-Level Schematic Entry with Composer for the switch-level schematic.

1.  Verilog simulator imposes two severe constraints on the logic style for switch-level schematic diagrams. The constraints for a switch-level schematic diagram are:

• Current should flow only in one direction for a transistor. It means that the drain and the source of each transistor are to be fixed in the schematic diagram.
• It seems that high impedance Z is not defined. Hence, transmission gates cannot be simulated properly.

2.  Move to your working directory. Edit the library path file, cds.lib, if necessary. Invoke Cadence software by typing

icfb&

3.  In Command Interface Window (CIW), select the following menus:

file -> open ...

• A new window appears. Set the following items, and click OK.
  • Library Name: MOSIS
  • Cell Name: My_Mux
  • View Name: schematic

4.  In Composer Window, select the following menus.

Tools -> Simulation -> Verilog-XL

• A new window appears. Verify Run Directory is "My_Mux.run1", and click OK.

5.  In Verilog window, select the following menus.

Stimulus -> STL -> Edit Stimulus...

• A window informing non-existent of the netlist appears, and click OK.

6.  Edit STL windows appear. Check "Compile STL after Editing?", and click OK.

• A text editor window appears. You should enter stimulus patterns in the file. Look for the line xv(0 0 0). This line means the first stimulus vector is (0 0 0) for the inputs defined in the top part of the file. Add other stimulus vectors. For the 2x1 multiplexer with three inputs, enter the following vectors.
• xv(0 0 0)
• xv(0 0 1)
• xv(0 1 0)
• ...
• xv(1 1 1)

7.  Save the file.

a.  A window asking "Do you want to make..." appears. Click YES.

b.  In Verilog window, click "Start Interactive" menu button which is on the top left in the menu. It starts to compile the netlist. Watch for any errors in the window.

c.  In Composer window, select all inputs and outputs to be monitored. To select multiple nodes, hold down SHIFT key, and encircle input/out pins as a group or individually.

d.  In Verilog window, click "View Waveforms" menu button which is on the bottom right in the menu. A waveform window with list of select I/Os appears.

e.  In Composer window, Click "Continue" menu button which is the right button on the second row.

f.  Examine the waveforms in "View Waveforms" window.

Have fun!

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