Chenyuan Zhao

302 Whittemore (0111)
Blacksburg, VA
24061

zcyg542@vt.edu

Degree Objective: Ph.D.

Resume: Seeking internship or cooperative education

Research Interests:

Analog IC Design for Brain inspired Computing

Education:

Ph.D. (cont’d), The Bradley Department of Electrical And Computer Engineering, Virginia Polytechnic Institute and State University (VT), (2017 – present)
Ph.D., Electrical Engineering and Computer Science, University of Kansas (KU), (2014 - 2017)
M.S., Information Science and Technology, JiNan University (JNU), China, (2012)
B.S., Automation, Nanjing University of Posts and Telecommunications (NJUPT), China, (2007)

Work Experiences:

Analog Circuits Design Engineer (internship) in ShenZhen BoChiXin Electronics CO. Ltd. (2010-2011)

Publications:

Google Scholar Profile
C. Zhao, Y. Yi, “When Energy Efficient Spike-Based Temporal Encoding Meets Resistive Crossbar: From Circuit Design to Application,” Neuromorphic Computing Symposium: Architectures, Models, and Applications (2017).
C. Zhao, J. Li, Y. Yi, “Energy efficient analog IC design for data compression in spiking neuromorphic systems,” IEEE/ACM Design Automation Conference (DAC) Work-in- Progress Session (2017).
C. Zhao, J. Li, and Y.Yi, “Inter-Spike Intervals (ISI) based Analog Spike-Time- Dependent Encoder for Neuromorphic Processors,” IEEE Transactions on Very Large Scale Integration (TVLSI) Systems (2017).
C. Zhao, J. Li, Y. Yi, “Analog Spiking Temporal Encoder with Inter-spike Intervals with Verification and Recovery Scheme for Neuromorphic Computing Systems,” IEEE International Symposium on Quality Electronic Design, (2017).
C. Zhao, B. Wysocki, C. Thiem, N. McDonald, J. Li, L. Liu, Y. Yi, "Energy Efficient Spiking Temporal Encoder Design for Neuromorphic Computing Systems," IEEE Transactions on Multi-Scale Computing Systems, vol. pp, no. 99 (2016).
C. Zhao, J. Li, and Y. Yi, “Novel Spike Based Reservoir Node Design with High Performance Spike Delay Loop,” in the Proceedings of ACM International Conference on Nanoscale Computing and Communication (2016).
C. Zhao, J. Li, and Y. Yi, “Making neural encoding robust and energy-efficient: an advanced analog temporal encoder for brain-inspired computing systems,” in the Proceedings of IEEE/ACM International Conference on Computer-Aided Design (2016).
C. Zhao, and Y. Yi, “Novel Spiking Temporal Encoder for Brain-inspired Computing Systems” IEEE/ACM Design Automation Conference (DAC) Work-in- Progress Session (2016).
C. Zhao, W. Danesh, B. T. Wysocki, and Y. Yi, “Neuromorphic encoding system design with chaos based CMOS analog neuron,” Computational Intelligence for Security and Defense Applications (CISDA), 2015 IEEE Symposium, pp. 1-6 (2015).
C. Zhao, B. T. Wysocki, Y. Liu, C. D. Thiem, N. R. McDonald, and Y. Yi, “Spike-Time-Dependent Encoding for Neuromorphic Processors,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 12, no. 3, pp. 23-40 (2015).
C. Zhao, J. Liu, F. Shen, and Y. Yi, “Low power CMOS power amplifier design for RFID and the Internet of Things,” Journal on Computers & Electrical Engineering, Elsevier (2015).
W. Danesh, C. Zhao, B. T. Wysocki, M. J. Medley, N. Thawdar, and Y. Yi, “Channel Estimation in Wireless OFDM Systems Using Reservoir Computing,” in Proceedings of IEEE Symposium on Computational Intelligence for Security and Defense Applications (CISDA), pp. 127-131 (2015).
C. Zhao, Z. Zhou, Y. C. Lee, Y. Yi, “Comprehensive Ultra-Broadband Design and Mode Suppression Techniques for Bends in a Differential Pair,” in Proceedings of Progress in Electromagnetic Research Symposium (PIERS), pp. 1998 (2014).
W. Huang, C. Zhao, W. Deng, J. Huang, “A New Low-Voltage CMOS Voltage Reference Design,” International Conference on Electric Information and Control Engineering (ICEICE), vol. 04, pp. 74-76 (2012).
C. Zhao, J. Huang, "A new high performance bandgap reference," International Conference on Electronics Communications and Control (ICECC), pp. 64-66 (2011).