Sign-Off (EDI, EPS, Primetime)

Author: Hetaswi Vankani, Adithya Venkatramanan, Dr. Dong S. Ha

NOTE: The files downloaded must not be saved or used in .txt format. Please save it in the format as mentioned in the tutorial.

1.  If the design is not already loaded in encounter. Cd into your project directory and type ‘Cadence’ followed by ‘encounter’ to load the encounter.

a.  Type ‘restoreDesign updown_counter_postRoute.enc.dat updown_counter’

b.  rcOut –view typical_view –spef updown_counter_dve_typical.spef

c.  writeTimingCon –sdc –view typical_view cnt_updown_syn_final.sdc

d.  cp /software/PDK/65nm_TSMC/Mosis_Doc/gds2.map

2.  Verify DRCs

a.  Verify → Verify Connectivity → Hit OK. The command prompt would display errors if any.

b.  Verify → Verify Metal Density → Hit OK. In case of this design, the min density is violated because the pads are placed at a distance.

c.  Verify → Verify Cut Density → Hit OK. The command prompt would display errors if any.

d.  Quick timing check:

i.  Timing → Report Timing → Design Stage: Post-Route, Analysis Type: Setup.

ii.  Timing → Report Timing → Design Stage: Post-Route, Analysis Type: Hold.

3.  Timing Sign-off using Primetime

a.  source pt_setup.tcl
This is meant to set paths to various target libs. If you haven’t done, the Synopsys front-end tutorial, compile libraries using lc_shell following instructions in tutorial on analyze and compile. Pt_setup.tcl can be downloaded from here: pt_setup.tcl.

i.  read_verilog ./updown_counter_postRoute.enc.dat/updown_counter.v.gz

ii.  read_parasitics –format spef ./updown_counter_dve_typical.spef

iii.  read_sdc ./cnt_updown_syn_final.sdc

iv.  report_timing –nosplit –capacitance –path_type full_clock –significant_digits 4 –delay_type max
Positive slack means that there is no setup error.

v.  report_timing –nosplit –capacitance –path_type full_clock –significant_digits 4 –delay_type min
Positive slack means that there is no hold error.

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