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Introduction

Digital Design Flow

 

Contents

  1. Front-End
  2. Back-End
  3. Sign Off

 

Front-End


  • Compile and Simulate: Use of Synopsys Verilog Compiler Simulator (VCS®) and its Discovery Visualization Environment (DVE®)  to analyze, compile and simulate an example up-down counter
  • Synthesis: Convert the Verilog code into gate-level netlist using Design Vision. This also includes an early power estimation step.

 

Back-End


  •  Physical Implementation: Floorplanning to place and route of a test circuit using Cadence’s Encounter Digital Implementation.

 

Sign-Off


  •  Sign-Off: Final DRC/LVS check, extraction, timing closure, IR drop and power analysis and conversion to GDSII.

 



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