Netlisting and Compiling

In the following part of the tutorial, you will use the AMS environment to netlist, compile, elaborate and simulate the design. (You can also run the script “run_amsdesigner” that compiles, elaborates, and simulates thedesign using the textual descriptions of the components without using the AMS enrionment. Please refer to the Cadence AMS Environment User Guide for more details.)

1. Opening the Command Interpreter Window

By typing icms at the command line from the previous step, you will open the Command Interpreter Window (CIW) shown in Figure 1. You can use this window to control the design session.

Figure 1. Cadence Command Interpreter Window

2. Opening the Schematic and Design Configuration

Open the schematic and design configuration by using the following steps.

a) In the CIW, choose Tools – Library Manager to open the Library Manager as shown in Figure 2:

Figure 2. Library Manager

b) In the Library column, click VFS_AMS_PHY180_sims to show all the cells in that library.

c) In the Cell column, click aeq_ac_sim to show all the views in that cell.

d) In the View column, double-click config_ams. The Open Configuration or Top CellView form appears.

Figure 3. Open Configuration or Top CellView Form

e) Select yes to open the Configuration and yes to open the Top Cell View.

f) Click OK. The Cadence hierarchy editor appears, displaying the aeq_ac_sim config view, shown in Figure 4 and the Virtuoso schematic editor appears, displaying the aeq_ac_sim schematic view shown in Figure 5.

Figure 4. The aeq_ac_sim config view in Cadence Hierarchy Editor

Figure 5. The aeq_ac_sim schematic view

3. Netlisting and Compiling with AMS Design Prep

a) Before using AMS Design Prep, use the following steps to install the AMS menu entry and specify a run directory and the location of two files used by AMS Designer. In the hierarchy editor, choose Plug-Ins – AMS. The menu bar changes to include the AMS entry, as shown in Figure 6. The AMS menu contains controls for the AMS environment and simulator.

Figure 6. Including AMS entry

i) Choose AMS – Run Directory, the AMS Run Directory form appears, shown in Figure 7.

Figure 7. AMS Run Directory Form

ii) Turn on Create new run directory. Turn on Create from current values in the AMS forms.

iii) In the New run directory field, change aeq_ac_sim_run to tutorial_run. (Leave the rest of the path intact.) Click OK. The other entries in the AMS menu become active.

iv) In the hierarchy editor, choose AMS – Options – Compiler. The AMS Options form appears, displaying the Compiler pane, shown in Figure 8.

Figure 8. AMS Options Form

v) Click Browse and the Select hdl.var File browser appears. Select the hdl.var file in the vfs_amsflow directory as shown in Figure 9.

Figure 9. Select the hdl.var file

vi) Click OK and the browser closes. Your hdl.var selection appears in the hdl.var file field of the Compiler pane. Click OK.

b) Run AMS Design Prep by using the following steps.

i) In the hierarchy editor, choose AMS – Design Prep. The AMS Design Prep form appears.

Figure 10. AMS Design Prep Form

ii) Turn on Netlist and All. These choices tell AMS Design Prep to netlist all the cellviews to make sure that everything is up to date. If switching to Incremental, only changed schematics are netlisted.

iii) Turn on Compile and All cellviews. These choices tell AMS Design Prep to compile everything during this first run, ensuring that all the compilations are up to date. If switching to When netlisting, only changed netlists are compiled.

iv) Click Run, which runs AMS Design Prep.

If the following message appears, click Yes.

The cds_globals module appears to have been modified outside of AMS Prep.... Continue processing and overwrite the cds_globals module?

If the following message appears, click Yes.

The configuration has been modified. Do you want to update and save the configuration before running Design Prep?

v) After AMS Design Prep finishes running, the Summary window appears. Click OK.

vi) If you want to view the newly created netlist like the BOND schematic, in the Cadence hierarchy editor Cell Bindings section, find the row for the BOND cell. Right-click on the row, to display the pop-up menu as shown in Figure 11. Choose View AMS Netlist. The netlist appears in a window. When you are done viewing the netlist, quit from the netlist without saving.

Figure 11. View AMS Netlist

vii) If you want to examine the values assigned to design variables, in the hierarchy editor, choose AMS – Design Variables. The AMS Design Variables form appears shown in Figure 12. Look over the list of variables and values. These values help characterize the design. They are all set appropriately so there is no need to change them. Click Cancel.

Figure 12. The AMS Design Variables Form

c) Specify the location of the model file by using the following steps.

i) In the hierarchy editor, choose AMS – Analog Models. The AMS Analog Models form appears shown in Figure 13.

Figure 13. The AMS Analog Models Form

ii) Ensure that the Analog Models tab is selected, highlight row 1, then click Browse. The Select Analog Model File browser appears. Starting in the vfs_amsflow directory, select the spectre_models/gpdk.scs file, as shown in Figure 14.

Figure 14. Analog Model File Selection

iii) Click OK to close the browser. Your selection appears in the Model File column of the AMS Analog Models form. In the Section column of the row containing the path to the gpdk.scs file, type NN. This selects the model designed to represent nominal operating conditions. With the same row highlighted, click Edit. The model file opens so you can review the files used to characterize the various operating conditions specified in the model file. When you are done of looking at the model file, quit without saving. In the AMS Analog Models form, click OK.

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