Elaborating and Simulating

Now that you have netlisted and compiled the entire design, you are ready to elaborate and simulate it. The AMS elaborator, ncelab, resolves disciplines, inserts interface elements, and creates a simulation snapshot of your design. The AMS simulator, ncsim, then runs the simulation.

(1) Specifying a Tcl File to Set SimVision Breakpoints
In the hierarchy editor, choose AMS – Options – Simulator. The AMS Options form appears, displaying the Simulator pane. Click Browse. The Select Tcl Script File browser appears, as shown in Figure 15.

Figure 15. Tcl Script File Selection

Select the demo.tcl file in the vfs_amsflow directory. Click OK to close the browser. The full path to your demo.tcl file appears in the Tcl input script field of the Simulator pane. This file sets a breakpoint to be used when SimVision runs. Click Apply.

 

(2) Specifying the Simulation Analysis
In the AMS Options form Categories pane, click Simulator – Analog Solver – Tran Analysis. The Tran Analysis pane appears. In the Stop time field, type 100n. Ensure that the Spectre Options tab is selected. In the Analysis title field, type tran1. After these steps, the Tran Analysis pane looks like Figure 16.

Figure 16. Setting up Transient Analysis

Click OK. The AMS Options form closes.

 

(3) Specifying Values to Save and Plot
In the hierarchy editor, choose AMS – Save/Plot. The AMS Save/Plot form appears as shown in Figure 17.

Figure 17. AMS Save/Plot Form

The first row in the table is a default setting for the entire design. Turning on Save and for row one is useful for small designs but saving all possible data slows down the simulation.

Click Schematic. The Virtuoso Schematic Editing window becomes active. It has a message at the bottom indicating that you can select objects to be saved and plotted. In the Schematic Editing window, select both the InP and InN net.

Figure 18.  Select the InP and InN net

Two new rows appear for the /InP and /InN net in the AMS Save/Plot form. Check both the Save and Plot columns for the two rows. Press Escape while you are still in the Virtuoso Schematic Editing window to end the selection of objects. The object selection message disappears from the Schematic Editing window and from the AMS Save/Plot form.

In the AMS Save/Plot form, click Navigator. The Scope Navigator form appears, displaying a hierarchical view of the design as shown in Figure 19.

Figure 19. Scope Navigator Form

Scroll down to the bottom of the Instance list, and highlight the dac6bit instance. The path to the instance appears in the Path field. Click OK. The Scope Navigator form closes. A new row appears in the AMS Save/Plot form with the path to the instance and default information for a new probe. Check both Save and Plot columns.

After these steps, the AMS Save/Plot form looks like this:

Figure 20. The AMS Save/Plot Form

 

(4) Elaborating the Design and Starting the Simulator
In the hierarchy editor window, choose AMS – Run Simulation. The AMS Run Simulation form appears as shown in Figure 21.

Figure 21. AMS Run Simulation Form

Ensure that the Simulation Setup tab is selected. Depending on the simulator you are using, the Cell field for Connect Rules specifies, by default, either mixedsignal or ConnRules_5V_full. These names are associated with the different sets of connect modules shipped with various releases of the simulator. In the Cell field for the Connect Rules, type ConnRules_18V_mid to replace the default value. Be sure that both Run Elaborator and Run Simulator are turned on. Click Run to elaborate the design and start the AMS simulator in GUI (interactive) mode, using the SimVision windows.

As the simulator starts, it opens the Console, Design Browser, and Waveform windows. This tutorial exercises only some of the basic features of SimVision. For detailed information, see SimVision User Guide.

In the Design Browser window, choose Windows – New – Source Browser. The Source Browser appears as Figure 22, showing the Verilog-AMS netlist for the aeq_ac_sim design.

Figure 22. Verilog-AMS netlist for the aeq_ac_sim design

You can hover over objects such as signals and see their values. For example, in the Source Browser, hold your cursor over DACOUT_INT at about line 21. Initially this analog value is zero, shown as in Figure 23:

Figure 23. Finding the Values of Objects in the Design

You can traverse the hierarchy by double-clicking on an instance. For example, in the Source Browser, double click on dac6bit at about line 20 to descend into the Verilog-A view of the 6-bit digital to analog converter. Click the Scope Up button, which is just to the right of the Scope field, shown in Figure 24.

Figure 24.  Traversing the Hierarchy in the Source Browser

 

(5) Running the Simulation
In the Waveform window, click the Run button and run the simulation until it ends at about simulation time 100ns. (You have to click Run twice to get past the 50ns breakpoint set in the demo.tcl file.) The waveforms appear as soon as they are calculated and continue marching during the remainder of the simulation. Choose View – Zoom – Full X and View – Zoom – Full Y to fit the waveforms into the available room in the Waveform window. Scroll down to the vout signal.

The vout signal is the reconstructed differential input of the analog to digital converter. This is the unfiltered DAC output so the edges look almost digital. The waveform shape has the expected amplitude and length, giving reassurance that the design is working as expected.

Figure 25. The vout signal in the Waveform window after simulation finishes

Choose Windows – Console. In the Console – SimVision window, find the information on CPU Usage. Note the user time you see here so that you can compare it later with the time required by the UltraSim solver. When you are done examining the waveforms, choose File – Exit SimVision.

 

(6) Plotting Waveforms After the Simulation Ends
In the hierarchy editor, choose AMS – Direct Plot. The AMS Direct Plot form appears as Figure 26. The Waveform window also appears.

Figure 26. AMS Direct Plot Form

Ensure that Function is set to Voltage and that Select is set to Net. These choices mean that the voltage is plotted each time you select a net from the schematic. The message

Select net from schematic …

appears at the bottom of the Virtuoso Schematic Editing window. In the Schematic Editing window, select the InP and InN net. Two corresponding plots of the voltage for the InP and InN net appear in the Waveform window.

 

In the AMS Direct Plot form, change Select to Differential nets. The message

Select positive net from schematic …

appears at the bottom of the Schematic Editing window. In the Schematic Editing window, select the InP net. The message

Select negative net from schematic …

appears at the bottom of the Schematic Editing window. Then in the Schematic Editing window, select the InN net. A waveform representing the difference of the voltages of the two nets is added to the Waveform window.

 

After these steps, the window looks like Figure 27:

Figure 27. The Direct Plot waveforms

When you are done examining the waveforms, choose File – Exit SimVision. In the AMS Direct Plot form, click OK. The form closes.

 

(7) Using the UltraSim Solver
In designs for which it is well suited, the UltraSim solver is faster and uses less memory than the Spectre solver, while maintaining near SPICE accuracy.

AMS Designer does not support using the UltraSim solver on designs that contain VHDL-AMS modules. You must remove or replace such modules before using the UltraSim solver. Switch out the VHDL-AMS module and switch in a corresponding Verilog-AMS module by using the following steps.

In the Cadence hierarchy editor Cell Bindings section, find the row for the VFS_AMS_PHY180.adc_ref_ladder cell. Right-click on the row, to display the pop-up menu. Choose Open. The file opens. In it, you see the entity and architecture of a VHDL-AMS module. When you are done of looking at the VHDL-AMS module, quit from the file without saving. Right-click on the same row again, to display the pop-up menu. Choose Set Cell View – verilogams as shown in Figure 28.

Figure 28. Set Cell View to verilogams

The name verilogams appears in the View to Use column, indicating that the Verilog-AMS view is to be used in place of the VHDL-AMS representation. Choose View – Update (Needed). The Update Sync-up message appears. Make sure that there is a check mark in the Select box for the VFS_AMS_PHY180_sims aeq_ac_sim config_ams cellview. Click OK. In the same adc_ref_ladder row, right-click to display to pop-up menu again. Choose Compile Netlist. The switched-in Verilog-AMS module is compiled and becomes ready for use.

 

(8) Switching to and Using the UltraSim Solver
In the Cadence hierarchy editor, choose AMS – Options – Simulator. The AMS Options window appears. In the Categories pane, choose Simulator – Analog Solver. The Analog Solver pane appears. In the Solver To Use area, select UltraSim. The UltraSim Options tab comes to the foreground in this form and in the other forms, such as the Convergence/Accuracy form, that have options for both solvers. Click OK.

Figure 29. Change the Analog Solver to UltraSim

In the Cadence hierarchy editor, choose AMS – Run Simulation. The AMS – Run window appears with the message
Data in the design hierarchy is out-of-date. Do you want to run Design Prep?
Click Cancel. Choose AMS – Design Prep. The AMS Design Prep window appears. Choose Netlist, Incremental, Compile, and When netlisting. These are efficient settings to use for AMS Design Prep during the cycles of development because only blocks that need netlisting are netlisted and compiled. Click Run. The AMS – Summary window appears showing zero values for all the entries. However, internal files used by AMS Designer are updated. Click OK. The Summary window closes.

In the Cadence hierarchy editor, choose AMS – Run Simulation. The AMS Run Simulation window appears. Ensure that the Simulation Setup tab is selected. In the Simulation Snapshot View field, append _US to the snapshot name. Without this change, the elaborator overwrites the Spectre solver snapshot. It is good idea to use a new snapshot name when you switch solvers so that you can reuse the first snapshot if necessary. Click Run. The SimVision windows appear.

In the Waveform window, click the Run button and run the simulation until it ends at about simulation time 100ns. (You have to click Run twice to get past the 50ns breakpoint set in the demo.tcl file.) The waveforms appear as soon as they are calculated and continue marching during the remainder of the simulation. Choose View – Zoom – Full X and View – Zoom – Full Y to fit the waveforms into the available room in the Waveform window.

In the Console – SimVision window, find the information on CPU Usage. Compare the user time you see here with the user time you noted earlier for the Spectre solver. For this configuration, the UltraSim solver typically finishes in about one third the time used by the Spectre solver.

When you are done with SimVision, choose File – Exit SimVision. In the Cadence hierarchy editor window, choose File – Exit. The hierarchy editor closes and releases the lock on the configuration file.

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