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Back End Design Using Cadence Tool – Physical Implementation

Authors: Hetaswi Vankani, Adithya Venkatramanan, and Dr. Dong S. Ha


Tool: Encounter Digital Implementation (encounter)

 

Clock Tree Synthesis

1.  Clock → Synthesize Clock Tree. A window as shown in fig 22 will appear.

Fig 22. Clock Tree Synthesis
Fig 22. Clock Tree Synthesis

2.  Hit (...). Select Clock.ctstch. Hit ‘OK’

3.  Route Design

a.  Route → Trial Route → Hit OK.

b.  Route → NanoRoute → Route → Hit OK

c.  Optimize → Optimize Design → Design Stage: Post-Route; Optimization type: setup and hold → Hit OK. The final layout of the design looks as in fig 23.

Fig 23. Final routed and optimized design layout.
Fig 23. Final routed and optimized design layout.

Authors: Hetaswi Vankani, Adithya Venkatramanan, and Dr. Dong S. Ha


Tool: Encounter Digital Implementation (encounter)

 

Floorplanning

1.  Core utilization: 0.72

2.  Core to left: 100; Core to right: 100; Core to top: 100; Core to bottom: 100

3.  Let all specifications be default.