Studying Scalability of Thermal-Resilient Hybrid Photonic-Electronic Networks-on-Chip

Speaker: Keyvan Ramezanpour

Host: MICS

Date: October 13 (Friday), 2017
Time: 2:30 PM - 3:30 PM
Location: Whittemore 654 (6th Floor Conference Room)

Abstract:

Scaling single-core processors faced complexities like high power density that forced designers to develop multi-core architectures and employ parallel processing to achieve higher performance. As a result, todays system-on-chips (SoCs) consist of numerous processing units (IP cores), including CPUs, GPUs and highbandwidth I/O along with large amounts of embedded memories. The conventional means of communication is the global bus architectures where all communicating cores share the same transmission medium. However, these architectures limit the number of cores connected to the communication medium and limits the scalability of the network. Networks-on-Chip (NoC) enable the integration of thousands of computing and storage resources in modern SoCs using communicationcentric approach for data transmission among IP cores.

The scalability of NoCs for future many-core systems is still challenging as the network delay and interconnect bottleneck, in highly scaled CMOS technology, limits the speed of data transfer among thousands of cores. Hybrid photonic-electronic NoCs are promising solutions to interconnect bottleneck of many-cores systems. Photonic interconnects for global links alleviates the delay of long electronic links, while, short distance connections are implemented with electronic links. Thus, Hybrid photonic-electronic networks-on-chip (HPENoCs) harness the strengths of both photonic and electronic links to meet the stringent demands of bandwidth, power, and latency of many-core systems. In this research the scalability of hybrid photonic-electronic NoCs with mesh architecture and thermal-resilient routing is studied. Microring resonators (MRRs), fundamental components in on-chip photonic networks, are highly sensitive to thermal variations, which may lead to erroneous optical transmission. Previously, we proposed a thermal-aware fault-tolerant routing technique (TAFT) to address this problem. In this paper, we examine and evaluate the scalability of TAFT as the NoC size grows. Organizing the NoC into different size clusters is a crucial part of TAFT scalability. Given the same number of cores, different cluster sizes can have up to 45% latency difference. The latency, throughput and power consumption are all dependent on cluster size, under similar traffic patterns. Simulation results also show that as the traffic pattern degrades, revising cluster size can yield up to 56% latency improvement.

Bio:

Keyvan Ramezanpour is a second year PhD studentat Virginia Tech. He completed undergraduate degree in Electrical Engineering, control systems, at University of Tabriz, Iran, and M.Sc. degree in communications systems at Sharif University of Technology, Iran, in 2007 and 2010, respectively. Synchronization of CDMA signals in the presence of multipath and implementing timing systems in wireless networks was part of his research. After working in the industry on implementing communications systems for low power embedded systems, he joined KU Leuven, Belgium, in 2012, to continue my studies in nanotechnology. He completed a master’s thesis on physics modeling of emerging III/V nanowire FET at IMEC, Belgium. He joined ECE department of Virginia Tech in 2016 for pursuing PhD degree, started working in the field of RFIC and studying the implementation of highly-efficient and linear power amplifiers for next generation 5G wireless networks. After a year, he continued his PhD research in the field of networks-on-chips for next generation heterogeneous computing platforms. His current research interests are reconfigurable clock distribution networks in many-core heterogeneous systemson-chip.