Introduction to CDR Circuit for Optical Communication

Speaker:  Joseph Chong

Host: MICS

Date: February 13 (Friday), 2015
Time: 3 PM - 4 PM
Location: Whittemore 654 (6th Floor Conference Room)

Abstract:

Clock and data recovery (CDR) circuit is the second block in an optical communication system, which role is to recover clock phase from random signal, and then re-time data to get non-distorted, clean data output. In this presentation, operation principles of CDR circuit will be briefly explained, and two types of phase detection scheme will be focused on: the linear (Hogge) and binary (Alexander) phase detector. The top to bottom introduction will include block diagrams as well as transistor level circuits. Recent literature on CDR circuit working above 20 Gb/s will also be presented.

Bio:

Joseph Chong received a B.S. and M.S. in Electrical Engineering from National Taiwan University, Taipei, Taiwan, in 2006 and 2008, respectively, where his research was on RFIC design. From 2008 to 2013, he worked at Wistron Corp on RF circuit design for consumer cellular products. He is now pursuing a PhD in Electrical Engineering at Virginia Tech. His current research interest is analog IC design on transceiver circuit for optical communication with 100Gbps serial data rate.