A 100 Gb/s CMOS transimpedance amplifier for high speed optical communication receivers

Speaker:  Joseph Chong (ECE, Virginia Tech)

Date: Friday, February 7, 2014
Time: 3 PM - 4 PM
Location: Whittemore 6th Floor Conference Room 

Abstract:

A 100 Gb/s transimpedance amplifier (TIA) in 65 nm CMOS technology is designed for high speed optical communication receivers. The proposed TIA is based on a differential architecture and composed of a regulated cascode block and a capacitive degeneration amplifier. It also adopts peaking inductors to increase the bandwidth. Post layout simulation results show that the TIA achieves 75 GHz bandwidth, 40.7 dBΩ transimpedance gain, ±4.3 ps of the group delay variation, and 25 pA/√Hz of the input referred noise current density. It dissipates 24 mW under supply voltage of 1.2 V. The proposed TIA increases the bandwidth by more than two times compared against other competing CMOS TIAs in the same technology, while achieving comparable performance.

Speaker:

Joseph Chong received the B.S. and the M.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2006 and 2008 respectively. He continued working on RF and high-speed digital circuit design until 2013. He is currently working toward the Ph.D degree in electrical engineering at Virginia Tech (VT).

His research interests focus on integrated circuit design for high-speed optical communication system.