A 3.25GHz Sampling Rate Charge Domain Coefficient Adjustable 4-Tap Analog FIR Filter

Speaker:  Shinwoong Park

Host: MICS

Date: October 3 (Friday), 2014
Time: 3 PM - 4 PM
Location: Whittemore 654 (6th Floor Conference Room)

Abstract:

This presentation is to demonstrate 3.25 GHz sampling rate analog FIR filter. Basically, FIR filter consists of addition and multiplication. This AFIR filter achieve multiplication by charge redistribution between two different sample and hold capacitor arrays. The multiplied values (voltage values) develop different currents through gm cell, then the currents are added together at a node. Finally, the total current is converted to voltage signal by resistive load. To implement 4 taps, 4 multiplier paths are used in different sampling phase. 2 different blocks of 4 multiplier paths make 2 coefficients and these coefficients are adjusted for bandwidth and gain. Advantage of the circuit includes coefficient flexibility, reduction of burden of ADC on the next stage, relaxed anti-aliasing requirements and low-power consumption.

Speaker:

Shinwoong Park received his B.S degree in Electrical engineering from University of Texas at Dallas in 2013. He is currently working towards PhD degree in electrical engineering at Virginia tech. He is currently working on Analog FIR Filter and PLL Divider. His research interest includes Mixed-mode circuits and systems for multifunctional RF systems..