Abstract:

Shrinking feature sizes of CMOS transistors has enabled increase in transistor densities, and this rising number of transistors increases the power consumption in ICs. Thus, the computing power is primarily constrained by power consumption and high-speed operation. Low-power consumption would imply lower heat dissipation, prolonged battery life and reduced cooling requirements, which all add up to significant reductions in cost and energy savings. Going forward, transistor scaling will require the introduction of new high mobility channel materials, including III-V and Ge, novel device architectures and their heterogeneous integration on highly dense Si CMOS could be a key enabler for lowering power consumption and enhance performance of microprocessor technology. According to the ITRS, channel materials with superior transport properties, high-k gate dielectric and multi-gate transistor configuration in a CMOS logic device under 10nm regime are required to achieve further increase in transistor drive current and resultant ULSI performance improvement. Beyond sub 22 nm technology node, high mobility III-V materials and new device architectures have the potential to provide higher switching speeds and to operate at lower voltage <0.5V than Si FETs. Heterogeneous integration of such high mobility materials with quantum well field effect transistor and tunnel FET architecture configuration have recently emerged a promising transistor option for ultra-high speed and low voltage operation. In this talk, I will present the recent development of the heterogeneous integration of compound semiconductors for n-channel and Ge for p-channel on Si and mixed As/Sb based type II staggered gap tunnel FETs research from our group.

Speaker:  

Dr. Mantu Hudait is an Associate Professor in the Bradley Department of Electrical and Computer Engineering (ECE), Virginia Tech. Prior to joining Virginia Tech, he was a Senior Engineer of the Intel Corporation's Advanced Transistor and Nanotechnology Group. His research at Virginia Tech focuses on heterogeneous integration of compound semiconductors and Ge on Si for ultra-low power and high-speed devices as well as multijunction photovoltaics. His breakthrough research in low-power transistor on Si at Intel Corporation was press released in 2007 and 2009. He has received two Divisional Recognition Awards from Intel Corporation, 38 US Patents issued, and over 120 technical publications. Dr. Hudait was responsible for the research and development of emerging nanoelectronic devices at The Ohio State University. He has received his PhD degree from Indian Institute of Science, Bangalore and MS degree from Indian Institute of Technology, Kharagpur. Dr. Hudait’s teaching focuses on integrating research and industry experience into the curriculum. He is a Senior Member of the IEEE Electron Devices Society, AVS member and ASEE member.