Power Estimation at the Gate Level Using Power Compiler

Power Estimation at the Gate Level
Using Power Compiler

Authors: Jinsik Yun, Jeannette Djigbenou, Dr. Dong S. Ha

This tutorial shows a power estimation using Power Compiler. This tutorial targets Verilog designs. You have to follow these instructions in order to minimize any setup errors. Note that this tutorial is based on the vtvt_tsmc180 library.

Using Design Compiler, you first need to generate a forward saif file. Then include the forward saif file in your testbench to generate a backward annotated saif file. Finally, read the backward saif file back to perform the power estimation.

1. Generate a forward saif file

Please downlod these sample two codes into <your_pjt_dir>:
- 4bit up-down counter: cnt_updown.v
- Verilog Testbench fot testing the 4bit up-down counter power: tb_cnt_updown_power.v
Generate a forward saif file for your design. Refer to the script cnt_updown_fw.scr
- Make sure that you have this command create_clock "clk" -name clk -period 10000 in the cnt_updown_fw.scr (Notes: 10000 is in ps units.)
  - Through this create_clock command, we can see the critical path briefly and optimize the clock skew
- Type dc_shell-xg-t in UNIX prompt. Design Compiler starts.
- Type source cnt_updown_fw.scr at the DC Shell prompt.
- The Verilog synthesized design cnt_updown_syn_power.v and the saif file cnt_updown_fw.saif of the counter are generated.
Analyze your synthesized design
- vlogan cnt_updown_syn_power.v
- vlogan tb_cnt_updown_power.v

2. Generate a backward saif file

Compile and elaborate your design, and set your simulation environment to call UCLI (Unified Command Line Interface) to run Verilog SAIF commands.
- vcs tb_cnt_updown -debug
- simv -ucli
The ucli prompt appears. You may now generate the backward SAIF file to get power estimation. Refer to the script cnt_updown_bw.scr
- Type source cnt_updown_bw.scr
- The backward saif file is generated: cnt_updown_bw.saif

3. Generate power estimation report

Synthesis of behavioral model with input toggle information. Refer to the script cnt_updown_power_dc_shell.scr
- Type 'dc_shell-xg-t' in UNIX prompt. Design Compiler starts.
- Type 'source cnt_updown_power_dc_shell.scr' at the DC Shell prompt.
- Power report is generated: power_toggle_dc_shell.rpt, the power unit is in uWatts
  - If you have a different module's report not your target module(in this tutorial "updown_counter" like the below, please refer to FAQ section