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Introduction

Synopsys Tutorials

 

Contents

  1. Front-End
  2. Digital Design Flow
  3. Others

 

Front-End


  • Compile and Simulate: Use of Synopsys Verilog Compiler Simulator (VCS®) and its Discovery Visualization Environment (DVE®)  to analyze, compile and simulate an example up-down counter
  • Synthesis: Convert the Verilog code into gate-level netlist using Design Vision. This also includes an early power estimation step.

 

Digital Design Flow


  • Digital Design Flow: Methodology for successful front-end design to back-end implementation of the chip at System on Chip (SoC) level. This involves using different tools from Synopsys and Cadence.

 

Others


 



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