Introduction

Synopsys Tutorials

Front-End

• Compile and Simulate: Use of Synopsys Verilog Compiler Simulator (VCS®) and its Discovery Visualization Environment (DVE®)  to analyze, compile and simulate an example up-down counter
• Synthesis: Convert the Verilog code into gate-level netlist using Design Vision. This also includes an early power estimation step.

Digital Design Flow

• Digital Design Flow: Methodology for successful front-end design to back-end implementation of the chip at System on Chip (SoC) level. This involves using different tools from Synopsys and Cadence.

Others

• Setting up your unix environment
• HSPICE: Analog SPICE Simulation
• NanoSim: Fast Analog SPICE Simulation