VCS - Verilog Logic Simulation Tool

VCS - Verilog Logic Simulation Tool

Authors: Jinsik Yun, Dr. Dong S. Ha

This tutorial shows a Verilog simulation process using VCS. You have to follow these instructions in order to minimize any setup errors. Note that this tutorial is based on the vtvt_tsmc180 library.

1. Analyze and Compile

• Please downlod these sample two codes into <your_pjt_dir>:
  
  • 4bit up-down counter: cnt_updown.v
    
  • Test bench fot the 4bit up-down counter: tb_cnt_updown.v
  
  For Instance, in my case <your_pjt_dir> is tutorial_synopsys as you see the below picture.
  
  
  
  
• Make sure that you have [Synopsys] prefix in your prompt like the above picture. If not, please type 'Synopsys' in order to get Synopsys environment path.
  
  
• Type these commands exactly as they are.
  • vlogan cnt_updown.v
  • vlogan tb_cnt_updown.v
  • vcs tb_cnt_updown
    (Please make sure that tb_cnt_updown is the top module name in this commands)
  Then you should see some messages like the below picture and you should have 'simv' executable file as the result of this command. Please refer to the below picture.
  
  
  
  

2. Execute Simulate

• Simply type 'simv' in your prompt. Then you can see some messages related to simulation results. Please refer to the below picture.
  
  
• You have to make sure that you have a newly generated 'updown_counter.dump' file in <your_pjt_dir>. The *.dump file is the waveform result.
  
  
  
  

3. Check the result waveform

• Type this command exactly as it is. 'vcs -RPP tb_cnt_updown'. '-RPP' means 'Run Post-Processing' mode. You can see the 'Virsim Hierarchy' window.
  
  
  
  
• Click 'File' menu in the 'Virsim Hierarchy' window.
  Then click 'Open...' submenu in the 'File' menu.
  
  
  
  Then you can see the 'Open File Dialog'
  
  
  
  
• Change 'Type' option to the 'VCD', not 'VCD+'. Then you can see the 'updown_counter.dump' file in the 'Files' list.
  
  
  
  
• Click the 'updown_counter.dump' file in the 'Files' list and click 'OK' button.
  
  
  
  
• You can see the 'tb_cnt_updown' was loaded in the 'Virsim Hierarchy' window.
  When you clikc the 'tb_cnt_updown' in the 'Hierarchy' list, you can see all signals defined in the source code.
  
  
  
• Press the 'New Waveform Window' graphic button in the 'Virsim Hierarchy' window. Then you can see the 'Waveform' window.
  
  
  
  
  
  
• You can select all signals in the 'Signals' tab and click the 'Add' button in the 'VirSim Hierarchy' window. (Or you can simply drag and drop all signals from the 'VirSim Hierarchy' window to 'VirSim Waveform' window by the middle button of mouse.)
  
  
  
  
  
  
•   Finally, you can zoom out all signals by click 'z%' button and click 100%. Then you can see all signals in the whole range.
  
  
  
  

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