Design Vision: A Logic Synthesis Tool

Author: Jinsik Yun, Jeannette Djigbenou, Dr. Dong S.Ha

This tutorial describes how to use Synopsys Synthesis tool, Design Vision, to generate a synthesized netlist of a design. To run this tutorial, you need a VHDL file which contains a behavioral description of the project you intend to design. Prior to this tutorial, it is recommended that you verify the logic of your design. To learn how to run logic simulation, please refer to the Logic Simulation Tutorial.

This tutorial shows a logic synthesis process for a 4-bit counter, which is described in the behavioral level. You must have setup your unix environment before this!!!

If you are using the standard cell libraries release package, start Synopsys using the Synopsys_Libraries directory of the release package. For directions on how to start Synopsys with the release package, please refer to the Synopsys Installation tutorial.

Copy an example of a 4-bit counter and a test bench for the counter into your working directory.

• • cnt_bhv.vhd 4-bit counter

  • tb_cnt_bhv.vhd Test bench for the counter

• Create subdirectory named 'work' under your current directory (if not already done). All intermediate files will be stored under the directory.

• Synthesis of the Behavioral Model

  • Type "Synopsys" at a UNIX prompt to start your Synopsis Environment.

  • Type "design_vision" at the Synopsis prompt. Design Vision will start in XG mode by default.

  • Design Vision window appears.

    • Click File -> Read... -> cnt_bhv.vhd -> OK

      • if you have “Can't read link_library file 'your_linbrary.db” warning, please refer to FAQ section

    • In the log window, make sure the message: “The Presto Compilation completed successfully” appears.

    • An item named CNT_BHV appears in Design Vision window under the Logical Hierarchy window. Select the item.

  • Click the “Create Design Schematic” icon on the main menu. The schematic displayed uses the Generic library symbols first.

• • Save the circuit in Verilog.

    • Click in Design Vision window.

    • File -> Save As... Save file windows appears.

    • Type the File Name as "cnt_syn.v" in the box.

      • NOTE: The file name should be different from the model file name. Otherwise, design_vision will overwrite the existing file.

      • NOTE: When you save the synthesized design as a Verilog file, you may want the brackets to be Verilog compatible; meaning “[ ]” instead of “< >”, which are the default bus delimiters. In order to do so, you can update the .synopsys_dc_setup file by modifying the bus naming variables as follows:
        

      • # Bus Naming variables
        • set bus_naming_style "%s[%d]"
        • set bus_dimension_separator_style "]["
        • set bus_range_separator_style ":"
        • set bus_extraction_style "%s[%d:%d]"
          

         

    • Select File Format as "Verilog" and click OK. (You can select other formats, if desired)

• If you wish to simulate the synthesized design, save the circuit as a VHDL file to verify the correct operation.

• When saving the synthesized design in the VHDL format for re-simulation, you may need to update the synthesized VHDL file and make sure the names of the libraries and packages are all matched. Once they are matched, you may then compile and pass running the vhdlan command.

  • Update the synthesized VHDL file:

     

    • Click in Design Vision window.
    • File -> Link Design... link design windows appears.

       

      
    • Confirm that your library is being set correctly as shown

    •  

      
    • Check in Design Vision Window>Design>Compile Design

• Perform the same procedure that is described in Sciroccos and VirSim – A Logic Simulation Tool with cnt_syn.vhd instead of cnt_bhv.vhd.

• The waveforms generated from cnt_bhv.vhd and cnt_syn.vhd should be same, because we are using the same testbench file, tb_cnt_bhv.vhd.

• Click in Design Vision window.

  • File -> Exit

Wasn’t that FUN!!!

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