Front End Design Using Synopsys Tool – Part 02 (dc_shell)
Author: Hetaswi Vankani, Adithya Venkatramanan, Dr. Dong S. Ha
12. Design → Compile Ultra → Check Retime and Exact Map → Hit OK
13. In the design_vision command prompt type
a. write_saif –output ./cnt_updown_dv_prop.saif –propagated
b. read_saif –input ./cnt_updown_dv_prop.saif –instance updown_counter
14. Reporting power
a. Design → Report Power → Hit OK
b. Exit the tool once power has been reported.
15. Saving the design:
a. File → Save
b. Save the design as cnt_updown_syn. Make sure that the format is selected as VERILOG ( not DEFAULT). After saving, double check if the synthesized netlist is available as cnt_updown_syn.v.
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