Paul Ampadu's Publications

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Year 2019

• K. Ramezanpour, and P. Ampadu, “FIMA: Fault Intensity Map Analysis,” in 10th International Workshop, COSADE 2019, pp. 63-79, April 2019.
• K. Ramezanpour, P. Ampadu, and W. Diehl, “A Statistical Fault Analysis Methodology for theAscon Authenticated Cipher,” in 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 41-50, May 2019.
• X. Liu, and P. Ampadu, “An Asymmetric Dual Output On-Chip DC-DC Converter for Dynamic Workloads,” in Proceedings of the 2019 on Great Lakes Symposium on VLSI, pp. 279-282, May 2019.
• M. F. Reza, and P. Ampadu, “Approximate Communication Strategies for Energy-Efficient and High Performance NoC: Opportunities and Challenges,” in Proceedings of the 2019 on Great Lakes Symposium on VLSI, pp. 399-404, May 2019.
• S. Ma, and P. Ampadu, “Approximate Memory with Approximate DCT,” in Proceedings of the 2019 on Great Lakes Symposium on VLSI, pp. 355-358, May 2019.
• B. Worek, and P. Ampadu, “Enabling Approximate Storage through Lossy Media Data Compression,” in Proceedings of the 2019 on Great Lakes Symposium on VLSI, pp. 327-330, May 2019.
• S. Ma, and P. Ampadu, “Optimal SAT-based Minimum Adder Synthesis of Linear Transformations,” in 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 335-338, Aug. 2019.
• S. Ma, and P. Ampadu, “Self-decompressing FPGA Bitstreams,” in 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 247-250, Aug. 2019.
• X. Liu, and P. Ampadu, “A Novel Single-Input-Multiple-Output DC/DC Converter for Distributed Power Management in Many-Core Systems,” in 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 794-797, Aug. 2019.
• M. F. Reza, and P. Ampadu, “Energy-efficient and high-performance NoC architecture and mapping solution for deep neural networks,” in NOCS '19 Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, pp. 12-19, Oct. 2019.
• K. Ramezanpour, and P. Ampadu, “Fault Intensity Map Analysis with Neural Network Key Distinguisher,” in ASHES'19 Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, pp. 33-42, Nov. 2019.
• K. Ramezanpour, and P. Ampadu, “RS-Mask: Random Space Masking as an Integrated Countermeasure against Power and Fault Analysis,” in 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Accepted (preprint).

Year 2018

• Ramezanpour, Keyvan, and Paul Ampadu. "Reconfigurable Clock Generator with Wide Frequency Range and Single-Cycle Phase and Frequency Switching." In 2018 31st IEEE International System-on-Chip Conference (SOCC), pp. 206-212. IEEE, 2018.
  

Year 2017

• D. Wolpert and P. Ampadu. "12 Ballistic Transistor Logic." Nanoelectronic Device Applications Handbook (2017): 143.
  
• K. Ramezanpour,  X. Liu, and P. Ampadu. "Improving Scalability in Thermally Resilient Hybrid Photonic-Electronic NoCs." Proceedings of the 10th International Workshop on Network on Chip Architectures (CFP: NoCArc). ACM, 2017.

Year 2016

• M. Yang, and P. Ampadu. "Thermal-Aware Adaptive Fault-Tolerant Routing for Hybrid Photonic-Electronic NoC." In Proceedings of the 9th International Workshop on Network on Chip Architectures, pp. 33-38. ACM, 2016.
  
• C. Li, M. Yang, and P. Ampadu. "An energy-efficient noc router with adaptive fault-tolerance using channel slicing and on-demand tmr." IEEE Transactions on Emerging Topics in Computing (2016).
  
• M. Yang, and P. Ampadu. "Energy-efficient power trimming for reliable nanophotonic noc microring resonators." In Circuits and Systems (ISCAS), 2016 IEEE International Symposium on, pp. 1682-1685. IEEE, 2016.
  

Year 2015

• C. Li, and P. Ampadu. "Energy-efficient NoC with variable channel width." In Circuits and Systems (MWSCAS), 2015 IEEE 58th International Midwest Symposium on, pp. 1-4. IEEE, 2015.
  
• C. Li, and P. Ampadu. "A compact low-power eDRAM-based NoC buffer." In Low Power Electronics and Design (ISLPED), 2015 IEEE/ACM International Symposium on, pp. 116-121. IEEE, 2015.

Year 2014

• M. Zhang, and P. Ampadu. "Two-layer error control codes combining rectangular and hamming product codes for cache error." Journal of Low Power Electronics and Applications 4, no. 1 (2014): 44-62.
  

Year 2013

• M. Zhang, and P. Ampadu. "Variation-tolerant cache by two-layer error control codes." In Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on, pp. 161-166. IEEE, 2013.
• C. Li, M. Zhang, and P. Ampadu. "Reliable ultra-low voltage cache with variation-tolerance." In Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on, pp. 121-124. IEEE, 2013.
  
• Q. Yu, M. Zhang, and P. Ampadu. "Addressing network-on-chip router transient errors with inherent information redundancy." ACM Transactions on Embedded Computing Systems (TECS) 12, no. 4 (2013): 105.
  
• P. Ampadu, M. Zhang, and V. Stojanovic. "Breaking the energy barrier in fault-tolerant caches for multicore systems." In Proceedings of the Conference on Design, Automation and Test in Europe, pp. 731-736. EDA Consortium, 2013.