Power Line Communications

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Year 2012

• J. Salem and D.S. Ha, “A Robust Receiver for Power Line Communications in Integrated Circuits,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 254-257, August 2012.

Year 2011

• R. Thirugnanam and D.S. Ha, "Feasibility Study for Communication over Power Distribution Networks of Microprocessors,” IEEE International SOC Conference, pp. 118-121, September 2011.
• V. Chawla and D.S. Ha, “Dual Use of Power Lines for Data Communications in Microprocessors,” IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 23-28, April 2011.

Year 2008

• V. Chawla, R. Thirugnanam, D.S. Ha, and T.M. Mak, "Design of a Data Recovery Block for Communications over Power Distribution Networks of Microprocessors,” International Conference on Circuits & Systems for Communications, pp. 708-712, May 2008.

Year 2007

• R. Thirugnanam, D.S. Ha, and T. M. Mak, "Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor," IEEE Computer Society Annual Symposium on VLSI, pp.153-158, May 2007.
• R. Thirugnanam, D.S. Ha, and T. M. Mak, “On Channel Modeling for Impulse-Based Communications over a Microprocessor's Power Distribution Network,” International Symposium on Power Line Communications, pp. 355-359, March 2007.

Year 2005

• W.C. Chung, and D.S. Ha, “A New Approach for Massive Parallel Scan,” International Test Conference, Paper 21.3, pp. 1-10, November 2005.
• W.C. Chung, D.S. Ha, and H.-J. Lee, “Dual Use of Power Lines for Data Communications in System-On-Chips Environments,”International Symposium on Circuits and Systems, pp. 3355–3358, May 2005.