Virginia Tech® home

ADS Layout Tutorial

Authors: Vipul Chawla and Dr. Dong S. Ha


5. Creating vias

Steps for via creation are similar to that of a component. In a two later PCB, hole layer is used to define a via. Via layout also contains masks for the metal layers that are interconnected through the via. These metal layers along with solder masks are used to define solder area for soldering the pin of a through-hole component. Also, Via connectivity need to be defined. This is done using via configuration menu. Click on Options ? Via configuration. In the via configuration window click on add via. Type via component name and add layers which are connected through the via. Save this configuration in the project directory. An example via configuration, interconnecting layers "cond" amd "cond2", is shown in figure 10.

 

ADS main window

Figure 11: Via configuration

Size of metal layers in a via should be chosen to be atleast 20% larger than the hole to allow for enough space for solder. The final via layout is shown in figure 11. We also need to add top and bottom layer solder mask[1] if the via is to be used for mounting a through-hole component on the PCB. However, if the via is just for interconnecting "cond" and "cond2" layers then solder mask is not required, as we are not going to solder any pin through the via.

Figure7

Figure 12: Via layout.

Save the via design like any other component. This via can now be used in another layout like any other component.

 

 

6. Interconnecting the components

Once the component footprints and vias have been created, the components can be organized to layout the complete design. However, depending upon the complexity of the design, a second level of hierarchy can be added. The design can be divided into modules and these modules can be later combined together in the top level layout.

Open a new layout and import the component footprints into the design. A component can be inserted by selecting Insert ? Component ? Component Library. A new "Component Library" window will open up. The components under the current project are listed under "All ? Sub-networks" library. Select the component to be imported and go back to the layout window to place the component. Footprints of additional components used in the example design in this tutorial are shown in figure 12.

 

a. Combined BNA+SMA footprint

SMA

b. SMA footprint

 

2-Pin

c. 2-pin strip

3-pin

d. 3-pin strip

Figure 13: Footprints of various components used in the example design.
 

The first step in laying out the top level design is to interconnect various components. Trace tool, available under "Insert ? Trace", should be used for drawing interconnect. While laying out a trace, one can switch between metal layers by hitting "," or "." Keys. Note that a via is automatically inserted at the point of layer change by the trace tool. Other layout tools available for interconnecting components are "Polygon", "Rectangle", and "Path", all available under "Insert" menu. Interconnects should overlap a bit onto the components to ensure that there are no gaps. The minimum interconnect trace width is usually dependent upon the frequency of operation of the circuit and also upon the manufacturing constraints. It is usually recommended to have the bottom layer as ground layer. Connections to the ground can thus be added by adding vias to the "cond2" layer. Top level layout with the completed interconnects is shown in figure 13. Note that ground pins have been added at multiple locations to provide ground contacts to the "cond2" layer. Also, labels have been added in the silkscreen layer to mark various I/O terminals.

Toplevellayout

Figure 14: Top level layout with completed interconnects.

A useful tool for laying out multilayer interconnects is the physical connectivity checker. Click on "Tools ? Check Connectivity ? Show Physical Interconnect" and then click on any routing or node to highlight the connectivity of interconnects. 


[1] Please note that ADS by default has only one solder mask layer, namely solder_mask, therefore a new solder mask layer needs to be defined for bottom layer solder mask.

 


Comments to: ha@vt.edu