###############################################################
#  Generated by:      Cadence Encounter 09.13-s229_1
#  OS:                Linux x86_64(Host ID cvlws07.cvl.ece)
#  Generated on:      Mon Nov 11 17:54:10 2013
#  Command:           clockDesign -genSpecOnly Clock.ctstch
###############################################################
#
# Encounter(R) Clock Synthesis Technology File Format
#

#-- MacroModel --
#MacroModel pin <pin> <maxRiseDelay> <minRiseDelay> <maxFallDelay> <minFallDelay> <inputCap>

#-- Special Route Type --
ClkGroup
+ clk_in

RouteTypeName CLK_ROUTE
TopPreferredLayer 4
BottomPreferredLayer 3

PreferredExtraSpace 0
End

AutoCTSRootPin clk_in
Period 1ns
MaxDelay 0.01ns
MinDelay 0ns
MaxSkew        40ps # sdc driven default
SinkMaxTran    150ps # sdc driven default
BufMaxTran     150ps # sdc driven default
MaxSkew 100ps
NoGating NO
#AddDriverCell CKBD16
Buffer CKBD8 CKBD16 CKBD20 CKBD24
NoGating NO
ExcludedPin
DetailReport YES
RouteClkNet YES
OptAddBuffer   YES
PostOpt YES
RouteType CLK_ROUTE
END



#PreferredExtraSpace 1
#End

#-- Regular Route Type --
#RouteTypeName regularRoute
#TopPreferredLayer 4
#BottomPreferredLayer 3
#PreferredExtraSpace 1
#End

#-- Clock Group --
#ClkGroup
#+ <clockName>