Dongseok Shin

302 Whittemore Hall
Blacksburg, VA
24060

dshin28@vt.edu

Resume

Ph.D. Student, Electrical and Computer Engineering, Virginia Tech, Blacksburg, USA, since Fall 2012 (Expected Graduation: Spring 2016)
M.S. in Electrical Engineering, Korea University, Seoul, Korea, 2006
B.S. in Electrical Engineering, University of Seoul, Seoul. Korea, 2004

2006. 07 – 2012.7 Circuit design engineer in Hynix Semiconductor Inc., Korea

Participated in designing GDDR3 SDRAM & GDDR5 DRAM(Graphic memory) and DDR2 SDRAM.
- Clock tree, DCC, RX and I/O sense amplifier design of 1Gb & 2Gb GDDR5 with 43nm and 54nm technology.
- DLL design of 512M DDR2 with 66nm technology.
- DLL and ODT design of 1G & 512M GDDR3 with 66nm technology.

D. Shin, J. Song, H. Che, K.-W. Kim, Y. Choi, and C. Kim, "A 7ps Jitter 0.053mm2 Fast Lock All-Digital DLL with Wide Range and High Resolution DCC," IEEE Journal of Solid-State Circuits, vol. 44, no. 9, pp. 2437-2451, Sep. 2009.
D. Shin, K.J. Na, D. Kown, J.H. Kang, T.Song, H.D. Jung, W.Y. Lee, K.C. Park, J.H. Park. Y.S. Joo, J.H. Cha, Y. Jung, Y. Kim, D. Han, B.J. Choi, G.I. Lee, J.H.Cho, and Y.J. Choi, "Wide-range fast-lock duty-cycle corrector with offset-tolerant duty-cycle detection scheme for 54nm 7Gb/s GDDR5 DRAM interface," IEEE Symposium on VLSI Circuits, Jun. 2009, pp. 138-139.
D. Shin, J.Koo, W.J. Yun, Y.J. Choi, and C. Kim, "A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-Digital Converter, " IEEE International Symposium on Circuits and Systems, May 2009, pp. 1-4.
D. Shin, W.J. Yun, H.W. Lee, Y.J. Choi, S.Kim, and C. Kim, "A 0.17-1.4GHz Low-Jitter All Digital DLL with TDC-based DCC using Pulse Width Detection Scheme," IEEE European Solid-State Circuits Conference, Sep. 2008, pp. 82-85.
D. Shin, J. Song, H. Che, K.-W. Kim, Y. Choi, and C. Kim, "A 7 ps Jitter 0.053 mm2 Fast-Lock All-Digital DLL with Wide-Range and High-Resolution All Digital DCC," IEEE International Solid-State Circuits Conference, Feb. 2007, pp.184-185.